This invention relates generally to microprocessors and their architecture for executing instructions and, more specifically, to the implementation of eXclusive OR (XOR) commands with equal operands.
As it is usually implemented, a microprocessor contains as part of its architecture a number of registers, generically called R0, R1, and so on. These commonly contain a set of general purpose registers to hold data or address quantities. An additional set of standard registers is known as the flags register. A collection of commands, the instruction set, controls the operation of the microprocessor.
The flags register consists of a number of small, usually one bit, subregisters, or flags, that control a number of conditional instructions and indicate the status of the processor. The microprocessor frequently needs to assign these flags values for conditional transfers, such as jump instructions, dependent upon the value of a certain flag. An example is the zero flag (ZF) that is set if the outcome of a particular instruction is zero. This flag is then consulted by subsequent operations if it should become important to determine if a particular operand is zero.
One of the basic members of the instruction set is the command XOR, the logical exclusive OR command. Since the logical result of XORing something with itself is 0, this device is commonly exploited as a way to clear registers. For example, the command xor r0,r0will get the content of the register R0 and XOR it with itself, producing a value of 0, which is then written back into R0, thus zeroing the register.
As a result of executing this command, the microprocessor must execute several further steps. It must note the outcome of the command and assign values to a number of flags accordingly, one of these being the zero flag that would be set to ZF=1. Thus to perform this common command and its attendant executions will require several steps, and therefore several clock cycles.
The consequences of this are particularly acute in a multiple pipeline microprocessor. Here, several commands are issued in parallel. This often results in some instructions having to wait as they may be dependent upon the outcome of another instruction. A familiar but relevant example of such a dependency, or data hazard, is the pair
xor r0,r1; R0.rarw.[R0]XOR [R1] PA1 add r0,r2; R0.rarw.[R0]ADD [R2],
where the ADD instruction depends on the outcome of the XOR and must wait for it to finish in that instruction's pipeline. Hence, when one instruction is paired with following dependent instructions, several pipelines may be stalled for one or more clock cycles.
Since the result of the XOR command with equal operands is known in advance, regardless of the actual contents of the register comprising that operand, this instruction results in the redundancies listed above. As this is a frequently employed technique, the resultant consumption of time and power can become significant.
It is the primary object of the present invention to reduce these limitations by decreasing the amount of redundancy in executing XOR instructions with equal operands.
It is another object to increase speed and reduce power consumption within a microprocessor.